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Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
64
Panasonic
ADM0ICH: Address 0 Match Interrupt Control Register (High) x’00FC7F’
ADM0ICH enables address match 0 interrupts. It is an 8-bit access regis-
ter. Use the MOVB instruction to access it.
The priority level for address match 0 interrupts is written to the
ADM3LV[2:0] field of the ADM3ICH register.
ADM0IE: Address match 0 interrupt enable flag
0: Disable
1: Enable
ANICL: A/D Conversion End Interrupt Control Register (Low) x’00FC80’
ANICL detects and requests A/D conversion end interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
ANIR: A/D conversion end interrupt request flag
0: No interrupt requested
1: Interrupt requested
ANID: A/D conversion end interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
ANICH: A/D Conversion End Interrupt Control Register (High) x’00FC81’
ANICH sets the priority level for and enables A/D conversion end inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
ANLV[2:0]: A/D conversion end interrupt priority level
Sets the priority from 0 to 6.
ANIE: A/D conversion end interrupt enable flag
0: Disable
1: Enable
Bit:76543210
———————
ADM0
IE
Reset:00000000
R/W:RRRRRRRR/W
Bit:76543210
———ANIR———ANID
Reset:00000000
R/W:RRRR/WRRRR
Bit:76543210
— ANLV2 ANLV1 ANLV0 — — — ANIE
Reset:00000000
R/W: R R/W R/W R/W R R R R/W