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2.4 D/I/O Architecture
disable\
input Latch
Clock input
D/O latch CKT
RESET\ (Sec. 3.3.1)
Data
(Sec. 3.3.8)
D/I/O
disable
Buffer input
Clock input
D/I buffer CKT
Data
(Sec. 3.3.8)
I/O select (Sec. 3.3.7)
• The RESET\ is in Low-state Æ all D/I/O are disabled
• The RESET\ is in High-state Æ all D/I/O are enabled
• If D/I/O is configured as D/I port Æ D/I= external input signal
• If D/I/O is configured as D/O port Æ D/I = read back D/O
• If D/I/O is configured as D/I port Æ send to D/O will change the D/O latch
register only. The D/I & external input signal will not change
OME-PIO-D96 User Manual (Ver.1.1, Mar/2003) ---- 8