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4.6 A/D Converter and Data FIFO
The DAQP card always assumes a bipolar input range of ±10V if the gain is one. The output
data format will always be in 2's complement (and left justified for 12-bit versions). The data
acquisition time of the A/D converter is 2 µs while it’s conversion time is no more than 8 µs.
The output of the A/D converter is fed into a data FIFO providing data buffering of up to 512
samples (2048 with 2K option installed).
The A/D converter, once triggered, will complete conversion for every analog input channel
specified in the scan list at the specified scan speed and then feed the results into the data
FIFO. In between scans, the DAQP card waits until another trigger is received (one-shot mode)
or the pacer clock fires (continuous mode).
The data FIFO has two programmable thresholds, one for almost full and the other for almost
empty. The DAQP card uses the almost full threshold and ignores the other one.
The data FIFO should always be flushed prior to using the arm/trig command to start data
acquisition. When the FIFO is flushed or emptied by the host reading its content, the FIFO
empty flag will be set. As long as there are samples left in the data FIFO, the empty flag will
be cleared.
When the number of data samples in the FIFO becomes greater than the programmed almost
full threshold, the almost full flag is set. When the number becomes less than or equal to the
specified almost full threshold, the flag will be cleared. On power up or reset, the threshold is
defaulted at 7 bytes to full (3.5 samples). Correct setting of the threshold will help achieve
optimal performance of the card.
When the FIFO is full, the full flag will be set, and no more samples can be written into the
FIFO. At the end of each scan, the DAQP card will set the data lost flag if the data FIFO is
already full. This flag will not be set before or during the scan, but at the end of it. Once the
data lost flag is set, it will not be cleared until the status register is read.
The data lost bit in the status register (base + 2) will be set when data continues to enter the
A/D data FIFO while it is already full. With the pre-trigger option, the data lost bit is also set
when an external trigger is received before the programmed data FIFO threshold is reached.
DAQP-208/208H/308 Users Manual 32