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Usin
g
your Pro
g
rammable Power Supply 5 - 27
There is a standard GPIB interface connector at the rear. The GPIB interface
software supports complete tri
gg
er capability.
If the tri
gg
er source = TIMer, the internal timer of the power supply is used to count
the interval time between two consecutive steps.
If the tri
gg
er source = EXTernal or BUS, the active tri
gg
er source depends on
whether or not the START line of the tri
gg
er bus at the rear is active.
EXTERNAL STEPPING (via the tri
gg
er bus)
If the START line is active (LOW), step pulses from the external STEP input
line will cause the next step to be performed.
EXTERNAL STEPPING (via the GPIB)
If the START line is not active (HIGH), the next step will be performed on the
receipt of the
*
TRG command or the GET code via the GPIB.
Note: LOW = 0 to 0.8V and HIGH = 2 to 5V
Tri
gg
er bus control:
External steppin
g
via the tri
gg
er bus can be done in two ways:
1) In the synchronous mode:
In this mode all three bus si
g
nal lines have their own functions.
2) In the asynchronous mode:
In this mode the READY line is externally connected to the START line.
To control the recall memory via the tri
gg
er bus, the STEP mode may not be
automatic, and the START input line must be pulled LOW. This will enable the
STEP line to tri
gg
er the next step to be executed (external tri
gg
erin
g
). Pullin
g
the
START line LOW will also disable the manual STEP key.
When enabled, a STEP pulse will tri
gg
er the step mechanism. The leadin
g
ed
g
e
of the STEP pulse makes the READY line active (LOW) within 100 nanoseconds.
The READY line will be released when the internal processin
g
is finished and the
STEP line is HIGH. The internal processin
g
time does not include the
repro
g
rammin
g
delay time. It is the responsibility of the user to choose a STEP
rate that is not too hi
g
h for the power supply and its load condition, so that the
output can settle within the STEP time.
Note: STEP pulses, received while the READY line is low, will be i
g
nored.