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1998 Feb 16 6
Philips Semiconductors Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
FUNCTIONAL DESCRIPTION
Demodulator
F
RAME SYNC PROTECTION
This circuit will detect the frame synchronization signals.
Two synchronization counters are used in the SAA7345:
1. The coincidence counter which is used to detect the
coincidence of successive syncs. It generates a Sync
coincidence signal if 2 syncs are 588 ±1 EFM clocks
apart.
2. The main counter is used to partition the EFM signal
into 17-bit words. This counter is reset when:
a) A Sync coincidence is generated.
b) A sync is found within ±6 EFM clocks of its
expected position.
The Sync coincidence signal is also used to generate the
Lock signal which will go active HIGH when 1 Sync
coincidence is found. It will reset to LOW when, during 61
consecutive frames, no Sync coincidence is found. This
Lock signal is accessed via the status signal when the
status control register (address 0010) is set to X100. See
section on “Microcontroller interface” .
Data Slicer and Clock Regenerator
The SAA7345 has an integrated slice level comparator
which is clocked by the crystal frequency clock. The slice
level is controlled by an internal current source applied to
an external capacitor under the control of the digital
phase-locked loop (DPLL).
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two microcontroller
control registers (addresses 1000 and 1001) for
bandwidth and equalization.
For certain applications an off-track input is necessary. If
this flag is HIGH, the SAA7345 will assume that the servo
is following on the wrong track, and will flag all incoming
HF data as incorrect. The off-track is input via the V1 pin
when the versatile pins interface register (address 1100)
bit 0 is set to logic 1.
EFM demodulation
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
Subcode data processing
Q-
CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal
buffer. Sixteen bits are used to perform a Cyclic
Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the status signal when the status control
register (address 0010) is set to X000 (normal reset
condition). Good Q-channel data may be read via the
microcontroller interface.
Fig.3 Data slicer showing typical application components.
47 pF
22 nF
2.2 kΩ
HFIN
HFREF
I
ref
ISLICE
22 kΩ
100 nF
2.2 nF
HF
input
crystal
clock
DQ
DPLL
1/2V
DD
V
SSA
V
SS
V
SSA
MGA368 - 1
V
DD
100 µA
100 µA