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1998 Feb 16 7
Philips Semiconductors Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
OTHER SUBCODE CHANNELS
Data of the other subcode channels (Q-to-W) may be read
via the V4 pin if the versatile pins interface register
(address 1101) is set to XX01.
The format is similar to RS232. The subcode sync word is
formed by a pause of 200 µs minimum. Each subcode byte
starts with a logic 1 followed by 7 bits (Q-to-W). The gap
between bytes is variable between 11.3 µs and 90 µs.
The subcode data is also available in the EBU output
(DOBM) in a similar format.
Microcontroller interface
The SAA7345 has a 3-line microcontroller interface which
is compatible with the digital servo IC TDA1301.
W
RITING DATA TO SAA7345
The SAA7345 has thirteen 4-bit programmable
configuration registers as shown in Table 2. These can be
written to via the microcontroller interface using the
protocol shown in Fig.5.
Write operation sequence
• RAB is held LOW by the microcontroller to hold the
SAA7345 DA pin at high-impedance.
• Microcontroller data is clocked into the internal shift
register on the LOW-to-HIGH clock transition CL.
• Data D (3 : 0) is latched into the appropriate control
register [address bits A (3 : 0)] on the LOW-to-HIGH
transition of RAB with CL HIGH.
• If more data is clocked into SAA7345 before the
LOW-to-HIGH transition of RAB then only the last 8 bits
are used.
• If less data is clocked into SAA7345, unpredictable
operation will result.
• If the LOW-to-HIGH transition of RAB occurs with CL
LOW, the command will be disregarded.
Fig.4 Subcode format and timing at V4 pin.
W96 1 Q1 R1 S1 T1 U1 V1 W1 1 Q2
200 µs
min
11.3
µs
11.3 µs min
90 µs max
MGA369
Fig.5 Microcontroller WRITE timing.
A3 A2 A1 A0 D3 D2 D1 D0
DA (SAA7345)
CL
(microcontroller)
RAB
(microcontroller)
DA
(microcontroller)
MGA379 - 1
high impedance