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S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1
11-5
TACON and TBCON are located in set 1, bank 1, at address E6H and E7H, and is read/write addressable using
Register addressing mode.
A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency
of fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation
by writing a "1" to TACON.3.
A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency
of fxx/512, and disables timer B interrupt. You can clear the timer B counter at any time during normal operation
by writing a "1" to TBCON.3.
To enable the timer A interrupt (TAINT) and timer B interrupt (TBINT), you must write TACON.7 to "0", TACON.2
(TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should write TACON.3
(TBCON.3) and TACON.0 (TBCON.0), which cleared counter and interrupt pending bit. When the TAINT and
TBINT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the
timer A and B interrupt pending bits, TACON.0 or TBCON.0.
Timer 1/A Control Register (TACON)
E6H, Set 1, Bank 1, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Timer A interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer A interrupt pending bit:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)
Timer A counter operating enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer A counter clear bit:
0 = No affect
1 = Clear the timer A counter (when write)
Timer A operating mode selection bit:
0 = Two 8-bit timers mode (Timer A/B)
1 = One 16-bit timer mode (Timer 1)
Timer A clock selection bits:
000 = fxx/512
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = fxt (sub clock)
110 = T1CLK (external clock)
111 = Not available
Figure 11-3. Timer 1/A Control Register (TACON)