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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08) 48 SMSC LAN9420/LAN9420i
DATASHEET
28 RESERVED
Host Actions: Cleared on writes and ignored on reads.
DMAC Actions: Ignored on reads. DMAC does not write to TDES1.
27 CK - TX Checksum Enable
if this bit is set in conjunction with the first segment bit (FS) in TDES1 and the TX checksum offload
engine enable bit (TX_COE_EN) in the checksum offload engine control register (COE_CR), the
TX checksum offload engine (TXCOE) will calculate an L3 checksum for the associated frame. The
16-bit checksum is inserted in the transmitted data as specified in Section 3.5.6, "Transmit
Checksum Offload Engine (TXCOE)," on page 63.
Host Actions: Initializes this bit.
DMAC Actions: Reads this bit to determine whether TXCOE should be enabled.
26 AC - Add CRC Disable
When set, the DMA Controller does not append the CRC to the end of the transmitted frame. This
field is valid only when first segment (FS - TDES1[29]) is set.
Host Actions: Initializes this bit.
DMAC Actions: Reads this bit to determine whether CRC should be appended to the end of the
transmitted frame.
25 TER - Transmit End of Ring
When set, indicates that the DMAC reached the final descriptor. Upon servicing this descriptor, the
DMAC returns to the base address of the DMA descriptor list pointed by the Transmit List Base
Address Register (TX_BASE_ADDR).
Host Actions: Initializes this bit.
DMAC Actions: Reads this bit to determine if this is the final descriptor in the ring.
24 TCH - Second Address Chained
When set, indicates that the second address in the descriptor is the next descriptor address, rather
than the second buffer address. When this bit is set, the TBS2 (TDES1[21:11]) must be all zeros.
TCH is ignored if TER (TDES1[25]) is set.
Host Actions: Initializes this bit.
DMAC Actions: Reads this bit to determine if second address is next descriptor address.
23 DPD - Disable Padding
When set, the DMA Controller does not automatically add a padding field to a packet shorter than
64 bytes. When cleared, the DMA Controller automatically adds a padding field and also a CRC
field to a packet shorter than 64 bytes. The CRC field is added despite the state of the add CRC
disable (AC - TDES1[26]) flag. This is valid only when the first segment (FS - TDES1[29]) is set.
Host Actions: Initializes this bit.
DMAC Actions: Reads this bit to determine if padding is enabled.
22 RESERVED
Host Actions: Cleared on writes and ignored on reads.
DMAC Actions: Ignored on reads. DMAC does not write to TDES1.
21:11 TBS2 - Transmit Buffer 2 Size
Indicates the size, in bytes, of the second data buffer. This field is not valid if TCH (TDES1[24]) is
set.
Host Actions: Initializes this field.
DMAC Actions: Reads this field to determine the allocated size of associated data buffer.
10:0 TBS1 - Transmit Buffer 1 Size
Indicates the size, in bytes, of the first data buffer. If this field is 0, the DMA controller ignores this
buffer and uses buffer2.
Host Actions: Initializes this field.
DMAC Actions: Reads this field to determine the allocated size of associated data buffer.
Table 3.10 TDES1 Bit Fields (continued)
BITS DESCRIPTION