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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 75 Revision 1.22 (09-25-08)
DATASHEET
3.7.3 Device Clocking
LAN9420/LAN9420i requires a fixed-frequency 25MHz clock source. This is typically provided by
attaching a 25MHz crystal to the XI and XO pins. The clock can optionally be provided by driving the
XI input pin with a single-ended 25MHz clock source. If a single-ended source is selected, the clock
input must run continuously for normal device operation.
Internally, LAN9420/LAN9420i generates its required clocks with a phase-locked loop (PLL). The
LAN9420/LAN9420i reduces its power consumption in the D3 state by disabling its internal PLL and
derivative clocks. The 25MHz clock remains operational in all states where power is applied.
Please refer to Section 5.9, "Clock Circuit," on page 166 for more information on clock requirements.
3.7.4 Power States
This section describes the operation of LAN9420/LAN9420i in each device power state (‘D’ states) as
well as the events required to cause state transitions. LAN9420/LAN9420i’s behavior is dependant on
the device’s VAUXDET pin (the device’s ability to detect wake events in D3
COLD
). Specific behaviors
are discussed in the sections that follow.
Device power states and associated state transitions are illustrated in Figure 3.28 below. Note that
Figure 3.28 includes the system’s mechanical off (G3) power state for illustrative purposes. This is the
G3 state as defined by the ACPI specification. In this state all power (+3.3V and 3.3Vaux) is off.
Some power state transitions may place the PHY in the General Power-Down state as noted in the
sections that follow. Please refer to Section 3.6.8.1, "General Power-Down," on page 72 for more
information on this mode of operation.
3.7.4.1 G3 State (Mechanical Off)
G3 is not a device power state, but is discussed here for illustrative purposes. In the G3 state all PCI
power is off. In this state all device context is lost.
3.7.4.1.1 POWER MANAGEMENT EVENTS IN G3
LAN9420/LAN9420i does not detect power management events in the G3 state.
Figure 3.28 LAN9420/LAN9420i Device Power States
D0
U
D0
A
D3
HOT
D3
COLD
T2
T4
T7
G3
Vaux Off
T1
T5,
T
8
T3
T6
T9
T12
T10
T11