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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 93 Revision 1.22 (09-25-08)
DATASHEET
Note 4.2 Default value is dependent on the state of the GPIO pin.
10:8 GPIO Direction 0-2 (GPDIRn)
When set, enables the corresponding GPIO as an output. When cleared the
GPIO is enabled as an input. Bits are assigned as follows:
GPIO0 – bit 8
GPIO1 – bit 9
GPIO2 – bit 10
R/W 000b
7:5 RESERVED RO -
4:3 GPO Data 3-4 (GPODn)
The value written is reflected on GPOn. Bits are assigned as follows:
GPO3 – bit 3
GPO4 – bit 4
R/W 00b
2:0 GPIO Data 0-2 (GPIODn)
When enabled as an output, the value written is reflected on GPIOn. When
read, GPIOn reflects the current state of the corresponding GPIO pin. Bits
are assigned as follows:
GPIO0 – bit 0
GPIO1 – bit 1
GPIO2 – bit 2
R/W Note 4.2
Table 4.3 EEPROM Enable Bit Definitions
[22] [21] [20] EEDIO FUNCTION EECLK FUNCTION
0 0 0 EEDIO EECLK
0 0 1 GPO3 GPO4
0 1 0 Reserved
0 1 1 GPO3 RX_DV
1 0 0 Reserved
1 0 1 TX_EN GPO4
1 1 0 TX_EN RX_DV
1 1 1 TX_CLK RX_CLK
BITS DESCRIPTION TYPE DEFAULT