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X7DBU/X7DGU User's Manual
J
W
O
R1
COM
2
J
7
JBT1
J
W
O
L1
JPL1
J
PL2
J
30
J
L1
J
OH1
J
D
1
F
an
2
LE
1
J
F1
F
P
CT
RL
J
PW
1
J
17
LE2
SW1
J11
I2C1
I2C2
J
PG1
Rear UID
E
S
10
0
0
V
id
e
o
CT
RL
Inte
l
E
S
B
2
(S
outh B
ridge
)
US
B4
J
W
D
J
K1
US
B2/3
J
18
S
MB
C
P
U1
J
PW
3
COM1
VGA
LAN1
LAN2
J
28
S
XB2:
PCI-E
x8
S
X
B1:
PCI-E
x16
PCI-X
133 M
Hz
(
Nor
t
h Br
idge)
Vid
e
o
M
e
m
o
r
y
X7DBU
J
29
F
an
4
F
an
8
CPU
F
A
N2
Fan3
F
an
1
20
-P
in
M
a
in
PW
R
J
PW
2
4-Pin
PW
R
8-Pin
PW
R
F
an
7
CPU
F
an
1
PW
R
S
M
B
Fa
n
5
F
a
n
6
Bu
zz
e
r
S
P1
J9B2
J9B1
J8B3
J8B2
J8B1
J7B3
J7B2
J7B1
D
IMM
4B
S
GPIO
1
S
GPIO2
J
27
UI
O
PW
R
LA
N
C
T
RL
J
LA
N2
J
LA
N
1
J
15
JCOM
1
JKM1
Bank1
I-S
A
T
A
0
I-SA
T
A
1
I-SA
T
A
2
I-
S
A
T
A
3
I-SA
T
A
4
I-
S
A
T
A
5
B
IO
S
J22
Flo
p
p
y
S
IM
S
O
ID
E
#
1
C
P
U2
J
P1
D
IM
M
1A
D
IMM
1B
D
IMM
2A
D
IMM
2B
D
IMM
3A
D
IMM
3
B
D
IMM
4A
Batt
e
r
y
Bank2
Bank3
Bank4
KB/MS
USB 0/1
J
5
J14
S
I/O
I
ntel 500
0
J
9
A
A. UID Switch
B. SGPIO1
C. SGPIO2
B
C
SGPIO Headers
There are two SGPIO (Serial General Purpose
Input/Output) headers (J29, J30) located on
the motherboard. These headers are used to
"talk to" the AMI Chip on the backplane. See
the table on the right for pin defi nitions. Refer
to the board layout below for the locations of
the headers.
SGPIO
Pin Defi nitions
Pin# Defi nition Pin Defi nition
1 *NC 2 *NC
3 Ground 4 Data
5 Load 6 Ground
7 *NC 8 *NC
Note: NC= No Connections
Unit Identifi cation Switches
There are two Unit Identifi cation (UID) Switches
on the motherboard. The Front Panel UID
Switch is connected to Pin 13 of the Front
Control Panel. The Rear UID Switch (SW1)
is located next to LAN Port2. When you
push the UID Switch on the Front Control
Panel, both Rear UID and FP UID Indicators
will turn on. Push the FP UID Switch (or the
Rear UID Switch-SW1) again to turn off both
Indicators. These UID Indicators provide easy
identifi cation of a system unit that may be in
need of service. (*For more information on
the FP UID Switch, please refer to FP UID
Switch on Page 2-11.)