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Chapter 4: BIOS
4-11
Memory Branch Mode
This option determines how the two memory branches operate. System address
space can either be interleaved between the two branches or Sequential from one
branch to another. Mirror mode allows data correction by maintaining two copies
of data in two branches. Single Channel 0 allows a single DIMM population during
system manufacturing. The options are Interleave, Sequential, Mirroring, and
Single Channel 0.
Branch 0/1 Rank Interleaving & Sparing
Select enable to enable the functions of Memory Interleaving and Memory Sparing
for Branch 0/1 Rank. The options for Memory Interleaving are 1:1, 2:1 and 4:1. The
options for Sparing are Enabled and Disabled.
Enhanced x8 Detection
Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options
are Disabled and Enabled.
High Temperature DRAM Operation
When set to Enabled, the BIOS will refer to the SPD table to set the maximum
DRAM temperature. If disabled, the BIOS will set the maximum DRAM temperature
based on a predefi ned value. The options are Enabled and Disabled.
AMB Thermal Sensor
Select Enabled to activate the thermal sensor embedded in the Advanced Memory
Buffer on a fully buffered memory module for thermal monitoring. The options are
Disabled and Enabled.
Thermal Throttle
Select Enabled to enable closed-loop thermal throttling on a fully buffered (FBD)
memory module. In the closed-loop thermal environment, thermal throttling will be
activated when the temperature of the FBD DIMM module exceeds a predefi ned
threshold. The options are Enabled and Disabled.
Global Activation Throttle
Select Enabled to enable open-loop global thermal throttling on a fully buffered
(FBD) memory module to make it active whenever the number of activate control
exceeds a predefi ned number. The options are Enabled and Disabled.
Crystal Beach Features
This feature was designed to implement Intel's I/O AT (Acceleration Technology) to
accelerate the performance of TOE devices. (Note: A TOE device is a specialized,
dedicated processor that is installed on an add-on card or a network card to handle
some or all packet processing of the add-on card. For this motherboard, the TOE
device is built inside the ESB 2 South Bridge chip.) The options are Enabled and
Disabled.