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2.3.1DeviceClockGeneration
2.3.2StepsforChangingPLL2Frequency
2.3.2.1DDR2ConsiderationsWhenModifyingPLL2Frequency
PLLController
PLLC2generatesclocksfromthePLL2outputclockforusebytheDDR2memorycontroller.Theseare
summarizedinTable7.
Table7.DDRPLLC2OutputClocks
OutputClockUsedbyDefaultDivider
SYSCLK1DDRPhy/2
SYSCLKBPDDRVTPController/2
TheSYSCLK1outputclockdividervaluedefaultsto/2.Assuminga25MHZMXI/CLKINandthePLL2
defaultmultiplierof×20,thisresultsina250MHZDDRPhyclock(125MHZDDR2).Itcanbemodifiedby
software(RATIObitinPLLDIV1)incombinationwithotherPLLmultiplierstoachievethedesiredDDR
clockrate.
ThePLLC2isprogrammedsimilarlytothePLLC1.Refertotheappropriatesubsectiononhowtoprogram
thePLL2clocks:
•IfthePLLispowereddown(PLLPWRDNbitinPLLCTLissetto1),followthefullPLLinitialization
procedureinSection2.3.2.2toinitializethePLL.
•IfthePLLisnotpowereddown(PLLPWRDNbitinPLLCTLisclearedto0),followthesequencein
Section2.3.2.3tochangethePLLmultiplier.
•IfthePLLisalreadyrunningatadesiredmultiplierandyouonlywanttochangetheSYSCLKdividers,
followthesequenceinSection2.3.2.4.
NotethatthePLLispowereddownafterthefollowingdevice-levelglobalresets:
•Power-onReset(POR)
•WarmReset(RESET)
•MaxReset
Inaddition,notethatthePLL2frequencydirectlyaffectstheDDR2memorycontroller.TheDDR2memory
controllerrequiresspecialsequencestobefollowedbeforeandafteryouchangethePLL2frequency.You
mustfollowtheadditionalconsiderationsfortheDDR2memorycontrollerinSection2.3.2.1inordertonot
corruptDDR2operation.
BeforechangingPLL2and/orPLLC2frequency,youmusttakeintoaccounttheDDR2memorycontroller
requirements.IftheDDR2memorycontrollerisusedinthesystem,followtheadditionalstepsinthis
sectiontochangePLL2and/orPLLC2frequencywithoutcorruptingDDR2operation.
•IftheDDR2memorycontrollerisinresetwhenyoudesiretochangethePLL2frequency,followthe
stepsinExample2.
•IftheDDR2memorycontrollerisalreadyoutofresetwhenyoudesiretochangethePLL2frequency,
followthestepsinExample3.
SPRUES0B–December2007Phase-LockedLoopController(PLLC)17
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