Filter
Top Products
www.ti.com
2.4.15ClockStatusRegister(CKSTAT)
PLLController
Theclockstatusregister(CKSTAT)isshowninFigure18anddescribedinTable24.CKSTATshows
clockstatusforallclocks,exceptSYSCLKn.
Figure18.ClockStatusRegister(CKSTAT)
3116
Reserved
R-0
1543210
ReservedBPONRsvdOBSONAUXON
R-0R-1R-0R-0or1
(1)
R-0or1
(2)
LEGEND:R=Readonly;-n=valueafterreset
(1)
ForPLLC1,OBSONdefaultsto1;forPLLC2,OBSONisreservedanddefaultsto0.
(2)
ForPLLC1,AUXONdefaultsto1;forPLLC2,AUXONisreservedanddefaultsto0.
Table24.ClockStatusRegister(CKSTAT)FieldDescriptions
BitFieldValueDescription
31-4Reserved0Reserved
3BPONSYSCLKBPonstatus.SYSCLKBPiscontrolledinthebypassdividerregister(BPDIV).
0SYSCLKBPisoff.
1SYSCLKBPison.
2Reserved0Reserved
1OBSONOBSCLKonstatus.OBSCLKiscontrolledintheoscillatordivider1register(OSCDIV1)andbythe
OBSENbitintheclockenablecontrolregister(CKEN).NotapplicableonPLLC2(thisbitisreserved).
0OBSCLKisoff.
1OBSCLKison.
0AUXONAUXCLKonstatus.AUXCLKiscontrolledbytheAUXENbitintheclockenablecontrolregister
(CKEN).NotapplicableonPLLC2(thisbitisreserved).
0AUXCLKisoff.
1AUXCLKison.
32Phase-LockedLoopController(PLLC)SPRUES0B–December2007
SubmitDocumentationFeedback