Texas Instruments TMS320C642x DSP Network Router User Manual


 
www.ti.com
2.3.2.4ChangingSYSCLKDividers
PLLController
ThissectiondiscussesthesoftwaresequencetochangetheSYSCLKdividers.TheSYSCLKdivider
changesequenceisalsoreferredtoasGOoperation,asitinvolveshittingtheGObit(GOSETbitin
PLLCMD)toinitiatethedividerchange.
1.CheckfortheGOSTATbitinPLLSTATtoclearto0toindicatethatnoGOoperationiscurrentlyin
progress.
2.ProgramtheRATIOfieldinPLLDIV1withthedesireddividefactor.Inthisstepmakesureyouleave
thePLLDIV1.D1ENbitset(default).
3.SettheGOSETbitinPLLCMDto1toinitiateanewdividertransition.Duringthistransition,SYSCLK1
ispausedmomentarily.
4.WaitforNnumberofPLLDIVnsourceclockcyclestoensuredividerchangeshavecompleted.Seethe
followingformulaforcalculatingthenumberofcyclesN.
5.WaitfortheGOSTATbitinPLLSTATtoclearto0.
ThefollowingformulashouldbeusedtocalculatethenumberofPLLDIVnsourceclockcycles:
N=(2×oldSYSCLK1dividevalue)+50cyclesoverhead
Example4.CalculatingNumberofClockCyclesN
ThisexamplecalculatesthenumberofclockcyclesN.
Settingsbeforedividerchange:
PLLDIV1.RATIO=1(divide-by-2)
Newdividersettings:
PLLDIV1.RATIO=2(divide-by-3)
Therefore,thenumberofcyclesNis:
N=(2×2)+50cyclesoverhead=54PLLDIVnsourceclockcycles
IfPLLC2isinPLLmode(PLLCTL.PLLEN=1),thePLLDIVnsourceclockisthePLL2outputclock.If
PLLC2isinPLLbypassmode(PLLCTL.PLLEN=0),thePLLDIVnsourceclockisthedeviceclock
sourceMXI/CLKIN.
20Phase-LockedLoopController(PLLC)SPRUES0BDecember2007
SubmitDocumentationFeedback