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2.4.4PLLMultiplierControlRegister(PLLM)
2.4.5PLLControllerDivider1Register(PLLDIV1)
PLLController
ThePLLmultipliercontrolregister(PLLM)isshowninFigure7anddescribedinTable13.
Figure7.PLLMultiplierControlRegister(PLLM)
3116
Reserved
R-0
15540
ReservedPLLM
R-0R/W-10hor13h
(1)
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
(1)
ForPLLC1,PLLMdefaultsto10h(PLLmultiplyby17);ForPLLC2,PLLMdefaultsto13h(PLLmultiplyby20).
Table13.PLLMultiplierControlRegister(PLLM)FieldDescriptions
BitFieldValueDescription
31-5Reserved0Reserved
4-0PLLM0-1FhPLLmultiplierselect.Multipliervalue=PLLM+1.Forexample,PLLM=16(10h)meansmultiplyby17.
Seedevice-specificdatamanualforvalidmultipliervaluesforeachPLL.
ThePLLcontrollerdivider1register(PLLDIV1)isshowninFigure8anddescribedinTable14.Divider1
controlsdividerforSYSCLK1.
Figure8.PLLControllerDivider1Register(PLLDIV1)
3116
Reserved
R-0
1514540
D1ENReservedRATIO
R/W-0R-0R/W-0or1
(1)
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
(1)
ForPLLC1,RATIOdefaultsto0(PLL1divideby1);forPLLC2,RATIOdefaultsto1(PLL2divideby2).
Table14.PLLControllerDivider1Register(PLLDIV1)FieldDescriptions
BitFieldValueDescription
31-16Reserved0Reserved
15D1ENDivider1enable.
0Divider1isdisabled.
1Divider1isenabled.
14-5Reserved0Reserved
4-0RATIO0-1FhDividerratio.Dividervalue=RATIO+1.Forexample,RATIO=0meansdivideby1.
24Phase-LockedLoopController(PLLC)SPRUES0B–December2007
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