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Data 2Data 1
HCS
HAS
HSTRB
HR/W
HCNTL[1:0]
HD[15:0]
HRDY
A
HHWIL
Internal
HPI latches
control information
Host latches
data
HPI latches
control information
Host latches
data
HPI Operation
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Figure 7. 16-Bit Multiplexed Mode Host Read Cycle Using HAS
A Depending on the type of write operation (HPID without autoincrementing, HPIA, HPIC, or HPID with
autoincrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more information, see
Section 3.9.
18
Host Port Interface (HPI) SPRUGK7A–March 2009–Revised July 2010
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