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1st halfword2nd halfword1st halfword2nd halfword1st halfword
Internal
HSTRB
HD[15:0]
HRDY
HHWIL
HR/W
HCNTL[1:0]
HCS
HPIA write HPID+ writes
00 or 10
HCNTL[1:0]
HD[31:0]
HRDY
HR/W
Internal
HSTRB
HCS
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HPI Operation
Figure 18. HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode
(Case 3: Autoincrementing Selected, FIFO Not Empty Before Write)
3.9.3 HRDY Behavior During 32-Bit Multiplexed Read Operations
Figure 19 shows an HPIC (HCNTL[1:0] = 00b) read or an HPIA (HCNTL[1:0] = 10b) read access for 32-bit
multiplexed HPI operation. Note that neither an HPIC nor an HPIA read access causes HRDY to become
active.
Figure 19. HRDY Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode
Figure 20 shows an HPIA (HCNTL[1:0] = 10b) write access followed by an HPID (HCNTL[1:0] = 11b) read
access for 32-bit multiplexed HPI operation.
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SPRUGK7A–March 2009–Revised July 2010 Host Port Interface (HPI)
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