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4.2Counter-CompareSubmoduleRegisters
Counter-CompareSubmoduleRegisters
Figure4-5.Time-BaseStatusRegister(TBSTS)
158
Reserved
R-0
73210
ReservedCTRMAXSYNCICTRDIR
R-0R/W1C-0R/W1C-0R-1
LEGEND:R/W=Read/Write;R=Readonly;R/W1C=Read/Write1toclear;-n=valueafterreset
Table4-5.Time-BaseStatusRegister(TBSTS)FieldDescriptions
BitFieldValueDescription
15:3ReservedReserved
2CTRMAXTime-BaseCounterMaxLatchedStatusBit
0Readinga0indicatesthetime-basecounterneverreacheditsmaximumvalue.Writinga0will
havenoeffect.
1Readinga1onthisbitindicatesthatthetime-basecounterreachedthemaxvalue0xFFFF.Writing
a1tothisbitwillclearthelatchedevent.
1SYNCIInputSynchronizationLatchedStatusBit
0Writinga0willhavenoeffect.Readinga0indicatesnoexternalsynchronizationeventhas
occurred.
1Readinga1onthisbitindicatesthatanexternalsynchronizationeventhasoccurred
(EPWMxSYNCI).Writinga1tothisbitwillclearthelatchedevent.
0CTRDIRTime-BaseCounterDirectionStatusBit.Atreset,thecounterisfrozen;therefore,thisbithasno
meaning.Tomakethisbitmeaningful,youmustfirstsettheappropriatemodevia
TBCTL[CTRMODE].
0Time-BaseCounteriscurrentlycountingdown.
1Time-BaseCounteriscurrentlycountingup.
Figure4-6throughFigure4-8andTable4-6throughTable4-8illustratethecounter-comparesubmodule
controlandstatusregisters.
Figure4-6.Counter-CompareARegister(CMPA)
150
CMPA
R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
SPRU791D–November2004–RevisedOctober2007Registers97
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