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Table 4–12. Isochronous Receive Channel Mask High Register Description (Continued)
BIT FIELD NAME TYPE DESCRIPTION
6 isoChannel38 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 38.
5 isoChannel37 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 37.
4 isoChannel36 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 36.
3 isoChannel35 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 35.
2 isoChannel34 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 34.
1 isoChannel33 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 33.
0 isoChannel32 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 32.
4.20 Isochronous Receive Channel Mask Low Register
The isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32
isochronous data channels. See Table 4–13 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Isochronous receive channel mask low
Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Isochronous receive channel mask low
Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC
Default X X X X X X X X X X X X X X X X
Register: Isochronous receive channel mask low
Type: Read/Set/Clear
Offset: 78h set register
7Ch clear register
Default: XXXX XXXXh
Table 4–13. Isochronous Receive Channel Mask Low Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 isoChannel31 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 31.
30 isoChannel30 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 30.
Bits 29 through 2 follow the same pattern.
1 isoChannel1 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 1.
0 isoChannel0 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 0.