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S1857 Trinity 371
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PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer. Burstable
transactions then burst on the PCI bus; nonburstable transactions do not.
PCI Master 0 WS Write
When this field is Enabled, writes to the PCI bus are executed with zero wait
states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transaction cycles. Select Enabled to support compliance with PCI specifica-
tion version 2.1.
PCI#2 Access #1 Retry
Select Enabled to rotate priority of PCI masters.
AGP Master 1 WS Write
Select Enabled to add one clock tick to AGP write operations.
AGP Master 1 WS Read
Select Enabled to add one clock tick to AGP read operations.
Assign IRQ for USB
Assign an IRQ number to the onboard USB port.
Assign IRQ for VGA
Assign an IRQ number to your VGA adapter.
Assign IRQ for ACPI
Assign an IRQ number to ACPI.
BIOS 2