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The Latching Buffers
The latching buffers are used only for state mode. The entire
PCI bus (except the clock) is latched in these buffers on the
rising edge of the PCI clock. The input to the latching buffers is
output port 1 from the input buffers. The latching buffers are IDT
162511 latching buffers with party generation. These buffers are
tri-stated in timing mode. In state mode their outputs go directly
to the logic analyzer input terminators.
The User pin signals are not latched.
The input to the logic analyzer consists of 3 parts.
The interface to the
Logic Analyzer
1. The RC terminators (90 ohm/10pf)
2. The 40 pin headers
3. The 40 pin cables
The user is instructed to remove the probe tip assemblies from
the logic analyzer headers. The 40 pin logic analyzer headers
then go directly the 40 pin headers of the Analysis Probe
provided cables. Any unused cables can be removed from the
Analysis Probe.
The logic analyzer provides the power to the onboard logic. No
power is obtained from the target.
The master clock is controlled by the front panel switches and is
generated by the on-board CPLD devices. When the user has
loaded the DEMULTIPLEXED configuration file an additional
Slave clock is added. This Slave clock is the falling edge of the
Analysis Probe generated AVALID signal. This signal asserts
with the first assertion of FRAME# and the rising edge of the PCI
clock. All of the PCI cycle bits are generated based on the
latched version of the PCI control signals. Their meaning is
listed in the following table.
The Clocking and Cycle
bit Generation Logic
Cycle bit name Function
EOFT_L - End of Transaction True for one clock cycle and indicates
the last cycle of a transaction
CPERR_L - Calculated Parity
Error
True for one clock cycle and indicates
that the on board parity logic has
detected a parity that is different than
the parity transmitted on the bus.
Please note that the Parity Checking
switch must be in the ON position.
MABORT_L - Master Abort True when a Master Abort condition has
been detected. Five clock cycles on a
single data transfer with no DEVSEL
assertion and six clock cycles on a
multi-beat transfer with no DEVSEL
asserted. Remains true for one clock
cycle.
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