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Using the Cycle bits
and L_CMD lines
Although the Cycle bit and the L_CMD lines were designed for
state analysis they can prove to be very useful in Timing
analysis. These bits can be effectively used to trigger the timing
analyzer. Note that the cycle bits and L_CMD lines pass through
more active logic than the PCI signals directly from the bus. For
this reason they may not line up exactly with the ADDR lines and
should not be used for precise timing measurements.
The demultiplexed feature of the PCI Active Analysis Probe is
not applicable to timing mode. Therefore for 32 bit timing mode
analysis does not require PODS 5 and 6 and 64 bit timing mode
analysis does not require PODS 9 and 10.
Demultiplexed
versus Multiplexed
If switching between demultiplexed state and timing mode those
PODS can be ignored when in timing mode. If doing only timing
mode the multiplexed files should be used.
Acquiring Data
Touch RUN and the logic analyzer will begin to acquire data.
The analyzer will continue to acquire data and will display the
data when the analyzer memory is full, the trigger specification is
TRUE or when you touch STOP.
The logic analyzer will flash “Waiting for Trigger” while the trigger
specification is NOT TRUE.
The Waveform
Display
Captured data is displayed as shown in the following figure.
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