Filter
Top Products
The Format Menu 17
The STAT variable 18
The ADDR, ADDR_B , ADDR_C, DATA_B and DATA variables 19
The BUS_UT variable 19
The L_CMD variable 19
Theory of Operation 20
The Input Buffers 20
The Latching Buffers 21
The interface to the Logic Analyzer 21
The Clocking and Cycle bit Generation Logic 21
The Data Parity Checking Logic 22
STATE ANALYSIS 23
Installation Quick Reference 23
Using the front panel switches in state mode 23
Acquiring Data 24
The State Display 24
Error Messages 25
INVASM OPTIONS 25
Setting up the Analyzer to use the PC Mapper Inverse Assembler 25
Acquiring Data 25
The State Display with the PCI PC Mapper 26
Error Messages 27
PCI PC Mapping for memory transactions 27
Interrupt Vector Table 28
PCI PC Mapping - I/O Transactions 30
TIMING ANALYSIS 33
Installation Quick Reference 33
Timing Mode Skew 33
Using the Cycle bits and L_CMD lines 34
Demultiplexed versus Multiplexed 34
Acquiring Data 34
3