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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Document #: 38-06070 Rev. *H Page 10 of 32
Figure 4. Counter, Mask, and Mirror Logic Block Diagram
[1]
From
Mask
Register
Mirror Counter
Address
Decode
RAM
Array
Wrap
1
0
Increment
Logic
1
0
+1
+2
1
0
Wrap
Detect
From
Mask
From
Counter
To
Counter
Bit 0
Wrap
17 17
17
17
17
1
0
Load/Increment
CNT/MSK
CNTEN
ADS
CNTRST
CLK
Decode
Logic
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
From
Address
Lines
To Readback
and Address
Decode
17
17
MRST
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