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Document #: 38-06070 Rev. *H Page 23 of 32
Figure 19. Counter Reset
[32, 33]
Switching Waveforms (continued)
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATA
IN
ADDRESS
CNTRST
R/W
DATA
OUT
A
n
A
m
A
p
A
x
0
1
A
n
A
m
A
p
Q
1
Q
n
Q
0
D
0
t
CH2
t
CL2
t
CYC2
t
SA
t
HA
t
SW
t
HW
t
SRST
t
HRST
t
SD
t
HD
t
CD2
t
CD2
t
CKLZ
[34]
RESET ADDRESS 0
COUNTER WRITE READ
ADDRESS 0 ADDRESS 1
READ READ
ADDRESS A
n
ADDRESS A
m
READ
Notes
32.CE
0
= B0 – B3 = LOW; CE
1
= MRST = CNT/MSK = HIGH.
33.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
34.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
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