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Document #: 38-06070 Rev. *H Page 11 of 32
Figure 5. Programmable Counter-Mask Register Operation
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2
16
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15
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6
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0
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0
H
H
L
H
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0s
1
0
1
0
101
00
Xs
1
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0
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0X0
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Xs
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1X1
00
Xs
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X
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X
0X0
Masked Address Unmasked Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
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