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MoBL-USB™ FX2LP18 USB Microcontroller
CY7C68053
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document # 001-06120 Rev *F Revised September 9th 2006
1.0 CY7C68053 Features
• USB 2.0 – USB-IF High-Speed and Full-Speed Compliant
(TID# 40000188)
• Single-chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
• Ideal for mobile applications (cell phone, smart phones,
PDAs, MP3 players)
— Ultra low power
— Suspend current: 20 µA (typical)
• Software: 8051 code runs from:
— Internal RAM, which is loaded from EEPROM
• 16 kBytes of on-chip Code/Data RAM
• Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• 8- or 16-bit external data interface
• Smart Media Standard ECC generation
• GPIF (General Programmable Interface)
— Allows direct connection to most parallel interface
— Programmable waveform descriptors and configuration
registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
• Integrated, industry standard enhanced 8051
— 48 MHz, 24 MHz, or 12 MHz CPU operation
— Four clocks per instruction cycle
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• 1.8V core operation
• 1.8V - 3.3V IO operation
• Vectored USB interrupts and GPIF/FIFO interrupts
• Separate data buffers for the Set-up and Data portions of a
CONTROL transfer
• Integrated I
2
C™ controller, runs at 100 or 400 kHz
• Four integrated FIFO’s
— Integrated glue logic and FIFO’s lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— Uses external clock or asynchronous strobes
— Easy interface to ASIC and DSP IC’s
• Available in Industrial temperature grade
• Available in one lead-free package with up to 24 GPIO’s
— 56-pin VFBGA (24 GPIO’s)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
Four Clocks/Cycle
I
2
C
VCC
1.5K
D+
D–
Address (16)/ Data Bus(8)
GPIF
CY
Smart
USB
1.1/2.0
Engine
USB
2.0
XCVR
16 KB
RAM
4 KB
FIFO
Integrated
Full- and High-speed
XCVR
Additional I/Os (24)
CTL (3)
RDY (2)
24 MHz
Ext. XTAL
Enhanced USB Core
Simplifies 8051 Code
“Soft Configuration”
Easy Firmware Changes
FIFO and Endpoint Memory
(master or slave operation)
General
Programmable I/F
Abundant I/O
High-performance micro
using standard tools
with lower-power options
Master
Connected for
Full-Speed
ECC
MoBL-USB FX2LP18
To Baseband processors/
Application processors/
ASICS/DSPs
8/16
Up to 96 MBytes/sec
Burst Rate
Block Diagram
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