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CYV15G0104TRB
Document #: 38-02100 Rev. *B Page 10 of 27
Phase-Align Buffer
Data from the Input Register is passed to the Phase-Align
Buffer, when the TXDB[9:0] input register is clocked using
TXCLKBA (TXCKSELB = 0) or when REFCLKB is a half-rate
clock (TXCKSELB = 1 and TXRATEB = 1). When the
TXDB[9:0] input register is clocked using REFCLKB±
(TXCKSELA = 1) and REFCLKB± is a full-rate clock
(TXRATEB = 0), the associated Phase Alignment Buffer in the
transmit path is bypassed. These buffers are used to absorb
clock phase differences between the TXCLKB input clock and
the internal character clock for that channel.
Once initialized, TXCLKB is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKB drifts beyond
the handling capacity of the Phase Align Buffer, TXERRB is
asserted to indicate the loss of data, and remains asserted
until the Phase Align Buffer is initialized. The phase of
TXCLKB relative to its internal character rate clock is initialized
when the configuration latch PABRSTB is written as 0. When
the associated TXERRB is deasserted, the Phase Align Buffer
is initialized and input characters are correctly captured.
If the phase offset, between the initialized location of the input
clock and REFCLKB, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on that
channel’s TXERRB output. This output indicates an error
continuously until the Phase-Align Buffer for that channel is
reset. While the error remains active, the transmitter for that
channel outputs a continuous “1001111000” character to
indicate to the remote receiver that an error condition is
present in the link.
Transmit BIST
The transmit channel contains an internal pattern generator
that can be used to validate both the link and device operation.
This generator is enabled by the TXBISTB latch via the device
configuration interface. When enabled, a register in the
transmit channel becomes a signature pattern generator by
logically converting to a Linear Feedback Shift Register
(LFSR). This LFSR generates a 511-character sequence. This
provides a predictable yet pseudo-random sequence that can
be matched to an identical LFSR in the attached Receiver(s).
A device reset (RESET
sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
All data present at the TXDB[9:0] inputs are ignored when
BIST is active on that channel.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLKB± input, and
that clock is multiplied by 10 or 20 (as selected by TXRATEB)
to generate a bit-rate clock for use by the transmit shifter. It
also provides a character-rate clock used by the transmit
paths, and outputs this character rate clock as TXCLKOB.
The clock multiplier PLL can accept a REFCLKB± input
between 19.5 MHz and 150 MHz, however, this clock range is
limited by the operating mode of the CYV15G0104TRB clock
multiplier (TXRATEB) and by the level on the SPDSELB input.
SPDSELB is a 3-level select
[4]
input that selects one of three
operating ranges for the serial data outputs of the transmit
channel. The operating serial signaling-rate and allowable
range of REFCLKB± frequencies are listed in Table 1.
The REFCLKB± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKB+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKB input, and leave the
alternate REFCLKB input open (floating).
When both the REFCLKB+ and REFCLKB– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKB– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKB+ input for alternate logic levels. When doing so, it
is necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Transmit Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
transmit shifter. These drivers have signal swings equivalent
to that of standard PECL drivers, and are capable of driving
AC-coupled optical modules or transmission lines.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both
transmit serial drivers are in this disabled state, the transmitter
internal logic for that channel is also powered down. A device
reset (RESET
sampled LOW) disables all output drivers.
Note. When the disabled transmit channel (i.e., both outputs
disabled) is re-enabled:
• the data on the transmit serial outputs may not meet all
timing specifications for up to 250 µs
• the state of the phase-align buffer cannot be guaranteed,
and a phase-align reset is required if the phase-align buffer
is used
CYV15G0104TRB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INA1± and INA2±, are
available on the receive channel for accepting serial data
streams. The active Serial Line Receiver is selected using the
Table 1. Operating Speed Settings
SPDSELB TXRATEB
REFCLKB±
Frequency
(MHz)
Signaling
Rate (Mbps)
LOW
1 reserved 195–400
0 19.5–40
MID (Open) 1 20–40 400–800
0 40–80
HIGH 1 40–75 800–1500
0 80–150
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