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CYV15G0104TRB
Document #: 38-02100 Rev. *B Page 9 of 27
CYV15G0104TRB HOTLink II Operation
The CYV15G0104TRB is a highly configurable, independent
clocking device designed to support reliable transfer of large
quantities of digital video data, using high-speed serial links
from multiple sources to multiple destinations.
CYV15G0104TRB Transmit Data Path
Input Register
The parallel input bus TXDB[9:0] can be clocked in using
TXCLKB (TXCKSELB = 0) or REFCLKB (TXCKSELB = 1).
ROE2A Internal Latch
[6]
Reclocker Differential Serial Output Driver 2 Enable.
ROE1A Internal Latch
[6]
Reclocker Differential Serial Output Driver 1 Enable.
PABRSTB Internal Latch
[6]
Transmit Clock Phase Alignment Buffer Reset.
Factory Test Modes
SCANEN2 LVTTL input,
internal pull-down
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as a NO
CONNECT, or GND only.
TMEN3 LVTTL input,
internal pull-down
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a NO
CONNECT, or GND only.
Analog I/O
TOUTB1± CML Differential
Output
Transmitter Primary Differential Serial Data Output. The transmitter TOUTB1± PECL-
compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
TOUTB2± CML Differential
Output
Transmitter Secondary Differential Serial Data Output. The transmitter TOUTB2± PECL-
compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines
or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
ROUTA1± CML Differential
Output
Reclocker Primary Differential Serial Data Output. The reclocker ROUTA1± PECL-
compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
ROUTA2± CML Differential
Output
Reclocker Secondary Differential Serial Data Output. The reclocker ROUTA2± PECL-
compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines
or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
INA1± Differential Input Primary Differential Serial Data Input. The INA1± input accepts the serial data stream
for deserialization. The INA1± serial stream is passed to the receive CDR circuit to extract
the data content when INSELA = HIGH.
INA2± Differential Input Secondary Differential Serial Data Input. The INA2± input accepts the serial data
stream for deserialization. The INA2± serial stream is passed to the receiver CDR circuit
to extract the data content when INSELA = LOW.
JTAG Interface
TMS LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high for
≥5 TCLK cycles, the JTAG test controller is reset.
TCLK LVTTL Input,
internal pull-down
JTAG Test Clock.
TDO 3-State LVTTL Output Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected.
TDI LVTTL Input,
internal pull-up
Test Data In. JTAG data input port.
TRST
LVTTL Input,
internal pull-up
JTAG reset signal. When asserted (LOW), this input asynchronously resets the JTAG
test access port controller.
Power
V
CC
+3.3V Power.
GND Signal and Power Ground for all internal circuits.
Pin Definitions (continued)
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer
Name I/O Characteristics Signal Description
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