Filter
Top Products
Dell
28
PowerEdge R210 II Technical Guide
8 Chipset
8.1 Overview
The PowerEdge R210 II planar incorporates the Intel C200 Series PCH chipset. The features listed
below are part of the chipset.
8.2 Direct Media Interface
Direct Media Interface (DMI) is the chip-to-chip connection between the processor and C200 series
chipset. This high-speed interface integrates advanced priority-based servicing allowing for
concurrent traffic and true isochronous transfer capabilities. Base functionality is completely
software-transparent, permitting current and legacy software to operate normally.
8.3 PCI Express Interface
The C200 series provides up to 8 PCI Express root ports. Each root port supports 5GT/s bandwidth.
PCI Express Root Ports 1-4 can be statically configured as four x1 ports or ganged together to form
one x4 port. Ports 5 and 6 can only be used as two x1 ports.
8.4 SATA Interface
The chipset has two integrated SATA host controllers that support independent DMA operation on up
to six port: 6 x 3Gb/s SATA. The SATA controller contains two modes of operation, a legacy mode
using I/O space and an AHCI mode using memory space. Software that uses legacy mode will not have
AHCI capabilities.
8.5 AHCI
The chipset provides hardware support for Advanced Host Controller Interface (AHCI), a new
programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of
performance features such as no master/slave designation for SATA devices—each device is treated
as a master—and hardware-assisted native command queuing. AHCI also provides usability
enhancements such as Hot-Plug. AHCI requires appropriate software support (for example, an AHCI
driver) and for some features, hardware support in the SATA device or additional platform hardware.
8.6 PCI Interface
The C200 Series chipset PCI interface provides a 33 MHz, Revision 2.3 implementation. The chipset
integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal
requests. This allows for combinations of up to 8 PCI down devices and PCI slots.
8.7 Low Pin Count (LPC) Interface
The LPC bridge function of the PCH resides in PCI Device 31: Function 0. In addition to the LPC bridge
function, D31:F0 contains other functional units including DMA, Interrupt controllers, Timers, Power
Management, System Management, GPIO, and RTC.
8.8 Serial Peripheral Interface (SPI)
The chipset implements an SPI Interface as an alternative interface for the BIOS flash device. An SPI
flash device can be used as a replacement for the FWH, and is required to support Gigabit Ethernet,