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EM78612
Universal Serial Bus Microcontroller
14 •
••
• Product Specification(V1.0) 03.22.2006
(This specification is subject to change without further notice)
0: Enable the wake-up function
R9 (Port 7 Wake-up Pin Selection Register) Default Value: (0B_1111_1111)
7 6 5 4 3 2 1 0
- - - - /Wu73 /Wu72 /Wu71 /Wu70
R9 [0 ~ 3] Select which of the Port 7 pins are to be defined to wake-up the MCU from
sleep mode. When the state of the selected pins changes during sleep
mode, the MCU will wake-up and execute the next instruction automatically.
1: Disable the wake-up function
0: Enable the wake-up function
RC (USB Application Status Register) Default Value: (0B_0000_0000)
7 6 5 4 3 2 1 0
EP0_W EP0_R EP1_R 0 Device_Resume Host_Suspend EP0_Busy Stall
RC [0] Stall flag. When MCU receives an unsupported command or invalid
parameters from host, this bit will be set to 1 by the firmware to notify the
UDC to return a STALL handshake. When a successful SETUP transaction
is received, this bit is cleared automatically. This bit is both readable and
writable.
RC [1] EP0 Busy flag. When this bit is equal to “1,” it indicates that the UDC is
writing data into the EP0’FIFO or reading data from it. During this time, the
firmware will avoid accessing the FIFO until UDC finishes writing or reading.
This bit is only readable.
RC [2] Host Suspend flag. If this bit is equal to 1, it indicates that USB bus has no
traffic for the specified period of 3.0 ms. This bit will also be cleared
automatically when a bus activity takes place. This bit is only readable.
This bit should be used in Dual Mode
RC [3] Device Resume flag. This bit is set by firmware to general a signal to
wake-up the USB host and is cleared as soon as the USB Suspend signal
becomes low. This bit can only be set by firmware and cleared by the
hardware.
This bit should be used in Dual Mode
RC [4] Undefined Register. The default value is 0.
RC [5,6] EP1_R / EP0_R flag. These two bits inform the UDC to read the data written
by firmware from the FIFO. Then the UDC sends the data to the host
automatically. After UDC finishes reading the data from the FIFO, this bit is
cleared automatically.