Filter
Top Products
Victoreen 875
Operators Manual
5-10
2. An auxiliary pulse from pin 3 of U208 to the automatic pulse generating circuits resets them so that
an automatically generated pulse will be present 17.1 minutes later if the ECS Test is not
conducted manually during that time. The purpose of this pulse is to insure continued operation of
automatic testing.
5.15 Outputs of U206 Pulse Generator on the ECS Board
We have noted that U206 can be triggered by pressing the ECS button. Its main output is a power pulse
to the ramp generator. However, it also initiates a pulse from U203 (pin 10) to pin 5 of U207A, the muting
multivibrator. The muting multivibrator also has two outputs:
1. One output to U203 that ultimately causes a muting pulse six seconds wide at terminal 9. This is
coupled to the power supply board on pin M. It also returns to the circuit so that jitters will be
eliminated on manual ECS.
2. A second output to U207 is a one-shot multivibrator that provides an enabling pulse to the latch
circuit (which also contains a flip-flop). The latch circuit consists of four NOR gate sections of U202
(pins 1 through 6 and 8 through 13), and also inverter U208 (pins 9 and 10). The latch circuit output
is taken from terminal 8, and will be either 6.2 V or 14 V. The operation is explained below.
5.16 Operation of the Latch Circuit
The latch circuit has two inputs and one output:
Input 1
- Enters on pin 6 (U202) and pin 10 (U208), which are connected. This is the monitoring input.
Its value is the result of the ECS Test. It enables the circuit to change state only after the conditions
brought about by the ECS Test have stabilized.
Input 2
- Enters pin 1 (U202) and pin 5 of U202 which are connected. The output is taken from pin 10
and pin 2 of U202, which are connected.
Output
- The output may be either 0 V, which is a pass indication, or +14 VDC, which is a fail indication.
The two NOR gates (pins 8, 9, 10, and pins 11, 12, 13) are effectively a flip-flop circuit which will
change its state only when a certain combination of the two inputs is present. The presence of CR201
and a pull-up circuit on the power supply printed circuit board permits pin 10 to be 0 while terminal 8 is
6.2 V.
Input 1 has a normal resting voltage of +15 V. However, during the ECS Test it takes on a voltage
determined by the steady detector current that exists during the ECS Test. This current generates a
voltage of about 2.57 V (0.33 scale) in the panel meter, at which time pin 6 of U202 is at approximately 0
V. If, at this instant, the enabling voltage (input 2) arrives, it will cause the flip-flop to switch states.
Input 2 is initiated by pressing the ECS button, but its actual occurrence in time is delayed so that it
occurs during the flat portion of the current cycle generated by the ECS ramp.
Assume that the green light is ON at the beginning of the ECS Test. Actually this is probable because:
If the green light were off, troubleshooting would not begin with the ECS Test. With this assumption we
can work backwards in the truth table (Table 5-1) from the output (which must be low) to the possible
inputs.
In Figure 5-2, the initial output is assumed low (circuit condition did not show fail prior to ECS Test).
When the enable pulse arrives in the two cases of the signal pulse [pass (L) or fail (H)] the following
conditions exist:
U202, pins 12, 10 L (Assumed as initial condition)