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SERIAL INTERFACE DEVELOPERS GUIDE
There are only a couple of registers that the host will typically modify. They are listed in the following
paragraphs.
6.9.1 FPA Processor Operational Control Register Low
Address: 0x4000
Bit 0 (Unit Gain): 0 – Use NUC Coefficient Memory Gain; 1 – Force NUC Gain to Unity (1.0)
Bit 1 (Zero Ofst): 0 – Use NUC Coefficient Memory Offset; 1 – Force NUC Offset to Zero
Bit 2 (Zero Rf Ofst): 0 – Use Utility Memory NUC Refresh Offset Coefficient; 1 – Force NUC Refresh
Offset to Zero
Bit 3 (Zero Px Rpl): 0 – Use NUC Coefficient Memory Pixel Replace Address; 1 – Force Defective
Pixels to Zero
Bit 4 (Cam Pwr Dwn): 0 – Normal Camera Operation; 1 – Force Camera Timing into Power Down
State (Set on power down detect interrupt)
Bit 6 (Act Itt Sel): 0 – Low ITT Applied to FPA Video; 1 – High ITT Applied to FPA Video
Bit 8 (Dspl Act): 0 – Blank FPA Image on Display; 1 – Enable FPA Image on Display
Bit 9 (Dspl Frz Mod): 0 – Normal (Live) FPA Image on Display; 1 –Freeze FPA Image on Display
(Previously Captured in Image Grab Buffer B)
Bit 10 (Dspl Zm Mod): 0 – 1X FPA Image on Display; 1 –2X FPA Image on Display
Bits 11-12 (Dspl Byte Sel): 0 – ITT/FB Bits 7:0 Displayed; 1 – ITT/FB Bits 15:8 Displayed; 2 – FB Bits
17:10 Displayed (when in Freeze Mode); 3 - Reserved
Bit 13 (Ovl Act): 0 – Disable Overlays on Display; 1 – Enable Overlays on Display
Bit 15 (Pfv Act): 0 – Disable Processed FPA Video Port Signals; 1 – Enable Processed FPA Video
Port Signals
6.9.2 FPA Processor Operational Control Register High
Address: 0x4001
Bit 0 (DFld Intr En): 0 – Disable Display Field Interrupt; 1 – Enable Display Field Interrupt
Bit 1 (FFrm Intr En): 0 – Disable FPA Frame Interrupt; 1 – Enable FPA Frame Interrupt
Bits 4-5 (EC Mem Dev Acc): 0 – No Memory Access; 1 - Instrumentation Header Memory Access; 2
– Color Palette Y Access; 3 – Color Palette Cr/Cb Access
Bits 8-9 (Tst Mux Sel): Test Mux Select: 0 – Digital FPA Video (Normal Operation); 1 – Test Count; 2
– Force 0; 3 – Force 1 (0x2000)
Bit 15 (Pfv FCnt En): 0 – Disable Processed FPA Video Frame Counter (Force to Zero); 1 – Enable
Processed FPA Video Frame Counter
6.9.3 FPA Processor User Mode Control Register
Address: 0x4002
Bits 0-1 (Mstr Sync Mod): 0 – Internal (Use Programmable Sync Generator); 1 – Reserved; 2 –
External (Field Toggle); 3 – External (Field Coherent)
Bit 6 (Dspl Vid Pol): 0 – Normal (“White Hot”); 1 – Inverted (“Black Hot”)
Bit 7 (Clr Bar En): 0 – Disable Display Color Bar; 1 – Enable Display Color Bar
Bit 8 (Clr Plt Y Sel): 0 – Low Byte of Color Palette Displayed (Normal Mode); 1 – High Byte of Color
Palette Displayed (Gamma Corrected)
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