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21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
6 Design Guide
The 21143 implements the 100BASE-T MII layer and the 100/10 Mb/s Ethernet MAC layer. The
21143 provides a dual network interface for both a 100BASE-T and a 10 Mb/s Ethernet. At the
100BASE-T port, the 21143 supports the industry-standard MII for any 100BASE-T
implementation.
The 21143 is fully compliant with the MII specifications (as defined in IEEE 802.3). The MII is a
nibblewide, general interface, that can be used with various physical interfaces, such as 100BASE-
TX, 100BASE-T4, shielded twisted-pair (STP), and fiber. It also supports dual rates of speed
(10 Mb/s and 100 Mb/s).
The 21143 includes special support for 100BASE-TX networks by including the PCS section
(scrambler and 5B/4B coding/decoding). Integrating the 10BASE-T ENDEC with the 100 Mb/s-
only SYM-based PHYs enables full support for a 10/100-implementation.
1.3 MII-Based PHY Block Diagram
Figure 1 is a block diagram of a 10BASE-T and 100BASE-T single-connector network connection
using a MII-based PHY device with the 21143.
MII-based PHY devices are provided by Intel, Integrated Circuit Systems*, National
Semiconductor*, Seeq*, and TDK*.
The MII-based PHY design includes the following components:
• The MII-based PHY devices, which have a direct interface to the MII port of the 21143 with
dual-rate option (as specified in the MII specification) and a full interface to the 10/100 Mb/s
magnetics module.
• The magnetics module, which is based on transformers and serial chokes enabling the network
connection to the 100 Mb/s network (100BASE-TX or 100BASE-T4) and to the 10 Mb/s
network (10BASE-T).
1.4 SYM-Based PHY Block Diagram
Figure 2 is a block diagram of a 100BASE-TX single-connector network connection using a SYM-
based PHY device with the 21143. For a 10 Mb/s network connection, the network can be
connected directly to the 21143 through filters and chokes.
Figure 1. MII-Based PHY Design
MII-Based
PHY
Devices
Magnetics
Module
10/100 Mb/s
Network
MII Port
of
21143