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102 536EX Chipset Developer’s Manual
Intel Confidential
Parallel Host Interface 16C450/16C550A UART
9.3 16C550A UART FIFO Operation
The modem 16C550A UART FIFO works in both interrupt and polled operation. A description of
each type of operation is provided below.
9.3.1 FIFO Interrupt Mode Operation
Both the modem receiver and transmitter UART FIFOs can be set up for interrupt mode operation.
The RCVR FIFO trigger level and character time-out interrupts have the same priority as the
current received data available interrupt. The XMIT FIFO empty interrupt has the same priority as
the Transmitter Holding register empty interrupt. Information pertaining to using the receiver and
transmitter FIFO interrupts is provided below.
1. When both the receiver FIFO and the receiver interrupts are enabled (FCR0 = 1, IER0 = 1), the
UART initiates RCVR interrupts under the following conditions:
a. The receive data available interrupt (IIR = 04) is issued to the DTE when the FIFO has
reached its programmed trigger level; the interrupt clears as soon as the FIFO drops below
the programmed trigger level
b. The data ready bit, DR (LSR0), is set as soon as a character is transferred from the
Internal Shift register to the RCVR FIFO. DR is reset when the FIFO is empty.
2. When the RCVR FIFO and receiver interrupts are enabled, the UART initiates a RCVR FIFO
time-out interrupt under the following conditions:
a. A RCVR FIFO time-out occurs when:
— At least one character is in the FIFO.
— The most recent serial character received was longer than four continuous character times
ago.
— The most recent DTE read of the FIFO was longer than four continuous character times
ago.
b. When a time-out interrupt has occurred, then it is cleared and the timer is reset when the
DTE reads one character from the RCVR FIFO.
c. The time-out timer is reset after a new character is received or after the DTE reads the
RCVR FIFO.
3. When the transmitter FIFO and the transmitter interrupt are enabled (FCR0 = 1, IER1 = 1), the
UART initiates XMIT interrupts under the following conditions:
a. The Transmitter Holding register interrupt (IIR = 02) occurs when the XMIT FIFO is
empty; it is cleared as soon as the transmitter holding register is written to or the IIR is
read. During servicing, the 1–16 character interrupt can be written to the XMIT FIFO.
9.3.2 FIFO Polled Mode Operation
Both the modem receiver and transmitter UART FIFOs can be set up for polled mode operation.
The UART FIFO is set for polled mode when FIFOE (FCR0) = 1 and the respective interrupt
enable bit (IER) = 0.
In polling mode, the DTE checks the LSR for receiver and/or transmitter status. The LSR register
provides the following information: