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536EX Chipset Developer’s Manual 99
Intel Confidential
Parallel Host Interface 16C450/16C550A UART
9.2.7 Interrupt Identity Register (IIR)
b
This read-only register indicates when the transmitter and receiver FIFOs are enabled, and the
source of highest-priority pending interrupt to the DTE. Five levels of modem interrupt sources in
order of priority are: receiver line status, received data ready, character time-out indication,
transmitter holding register empty, and modem status. When the DTE reads the IIR, the modem
freezes all interrupts and indicates the highest-priority pending interrupt. While the DTE is reading
the IIR register, the modem records new interrupts but does not change its current indication until
the read process is completed.
Figure 20. Interrupt Identity Register (IIR)
FIFO EN FIFO EN 0 VDMA Int. ID 2 Int. ID 1 Int. ID 0 Int. Pen.
Register 2
(read-only)
Table 28. Interrupt Control Functions
FIFO
Mode
Only
Interrupt
Identification
Register
Interrupt Source and Reset Functions
Bit 3
ID 2
Bit 2
ID1
Bit 1
ID0
Bit 0
Int.
Pend.
Priority
Level
Interrupt Type Interrupt Source Interrupt Reset Control
0001 – None None –
0 1 1 0 Highest
Receiver Line
Status
Overrun Error, Parity Error,
Framing Error or Break
Interrupt
Reading the LSR (Line
Status register)
0 1 0 0 Second
Received Data
Available
Receiver Data Available or
Trigger Level Reached
Reading the RBR (Receiver
Buffer register) or the FIFO
Drops below the Trigger
Level
1 1 0 0 Second
Character
Time-out
Indication
No characters have been
removed from or entered
into the RCVR FIFO during
the last four character times,
and there is at least one
character in it during this
time
Reading the RBR (Receiver
Buffer register)
0010 Third
Transmitter
Holding
Register
Empty
Transmitter Holding
Register Empty
Reading the IIR register (if
the source of interrupt) or
writing into the Transmitter
Holding register
0 0 0 0 Fourth Modem Status
Clear to Send,
Data Set Ready,
Ring Indicator, or Data
Carrier Detect
Reading the MSR (Modem
Status register)
Bits 7:6 FIFOs Enable Bits—These two bits are set whenever FCR0 = 1.
Bits 5 Not used—This bit is permanently set to ‘0’.
Bit 4 Reserved