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Software Developer’s Manual 13
Architectural Overview
Note: Refer to the Extended Device Control Register (bits 23:22) for mode selection (see Section 13.4.6).
The link can be configured by several methods. Software can force the link setting to Auto-
Negotiation by setting either the MAC in TBI
mode (internal SerDes for the 82546GB/EB and
82545GM/EM), or the PHY in internal PHY mode.
The speed of the link in internal PHY mode can be determined by several methods:
• Auto speed detection based on the receive clock signal generated by the PHY.
• Detection of the PHY link speed indication.
• Software forcing the configuration of link speed.
2.3.6 10/100/1000 Ethernet Transceiver (PHY)
The Ethernet controller provides a full high-performance, integrated transceiver for 10/100/
1000 Mb/s data communication. The physical layer (PHY) blocks are 802.3 compliant and capable
of operating in half-duplex or full-duplex modes.
Highlights of the PHY blocks are as follows:
• Data stream serializers and encoders. Encoding techniques include Manchester, 4B/5B and
4D/PAM5. These blocks also perform data scrambling for 100/1000 Mb/s transmission as a
technique to minimize radiated Electromagnetic Interference (EMI).
• A multi-mode transmit digital to analog converter, which produces filtered waveforms
appropriate for the 10BASE-T, 100BASE-TX or 1000BASE-T Ethernet standards.
• Receiver Analog-to-Digital Converter (ADC). The ADC uses a 125 MHz sampling rate.
• Receiver decoders. These blocks perform the inverse operations of serializers, encoders and
scramblers.
• Active hybrid and echo canceller blocks. The active hybrid and echo canceller blocks reduce
the echo effect of transmitting and receiving simultaneously on the same analog pairs.
• NEXT canceller. This unit removes high frequency Near End Crosstalk induced among
adjacent signal pairs.
• Additional wave shaping and slew rate control circuitry to reduce EMI.
Because the Ethernet controller is IEEE-compliant, the PHY blocks communicate with the MAC
blocks through an internal GMII/MII bus operating at clock speeds of 2.5 MHz up to 125 MHz.
The Ethernet controller also uses an IEEE-compliant internal Management Data interface to
communicate control and status information to the PHY.
2.3.7 EEPROM Interface
The PCI/PCI-X Family of Gigabit Ethernet Controllers provide a four-wire direct interface to a
serial EEPROM device such as the 93C46 or compatible for storing product configuration
information. Several words of the data stored in the EEPROM are automatically accessed by the
Ethernet controller, after reset, to provide pre-boot configuration data to the Ethernet controller
before it is accessible by the host software. The remainder of the stored information is accessed by
various software modules to report product configuration, serial number and other parameters.