Intel 82541xx Network Card User Manual


 
Software Developer’s Manual 287
Register Descriptions
Note: Careful attention to the IEEE 802.3z standard is required in order to meet specified timing
requirements for timing during a software negotiated link.
13.4.14 Receive Configuration Word Register
1
RXCW (00180h; R)
This register has meaning only in TBI/internal SerDes mode of operation. The RXCW register
records the partner abilities and provides indications about its Auto-Negotiation status.
The contents of this register depend on the state of TXCW.ANE. If ANE is set, then this register
records the 16-bit defined in IEEE 802.3z. When performing software Auto-Negotiation, software
should look for RXCW.ANC. When RXCW.ANC is set, the contents of RXCW.RxConfigWord are
valid, when RXCW.ANC is cleared, then the content of this register is undefined.
Note: While in internal SerDes mode (82546GB/EB and 82545GM/EM only), software might be
required to inspect or monitor the results of RXCW to generate a link up/down indication.
Field Bit(s)
Initial
Value
Description
TxConfig 30 0b
Transmit Config Control bit
0b = Transmit data/idle
1b = Transmit /C/ ordered sets
Setting the TxConfig bit causes transmission of /C/ ordered set in
a software controlled Auto-Negotiation process
(TXCW.ANE=0b).
ANE 31 0b
Auto-Negotiation Enable.
1b = Enable the hardware Auto-Negotiation state machine.
0b = Disable the hardware Auto-Negotiation state machine.
This bit has the same function as bit 0.12 defined in sub-clause
22.2.4.1.4 of the 802.3z standard. Since this bit is a “static”
value, a pulse is generated by hardware in response to writing
this bit with a 1b. This pulse is used to restart the Auto-
Negotiation state machine.
When ANE is set, a transition from loss of synchronization to
synchronized state restarts the Auto-Negotiation as well.
If ANE is cleared, then the Ethernet controller is performing
software Auto-Negotiation. In that case TxConfig and
TxConfigWord are used to negotiate with the link partner.
The ANE is loadable from the EEPROM upon power up or chip
reset.
1. Not applicable to the 82541xx, 82547GI/EI, or 82540EP/EM.