Intel S5000PSL Computer Hardware User Manual


 
Intel® Server Boards S5000PSL and S5000XSL TPS Glossary
Term Definition
IFB I/O and Firmware Bridge
INTR Interrupt
IP Internet Protocol
IPMB Intelligent Platform Management Bus
IPMI Intelligent Platform Management Interface
IR Infrared
ITP In-Target Probe
KB 1024 bytes
KCS Keyboard Controller Style
LAN Local Area Network
LCD Liquid Crystal Display
LED Light Emitting Diode
LPC Low Pin Count
LUN Logical Unit Number
MAC Media Access Control
MB 1024KB
MCH Memory Controller Hub
MD2 Message Digest 2 – Hashing Algorithm
MD5 Message Digest 5 – Hashing Algorithm – Higher Security
ms milliseconds
MTTR Memory Type Range Register
Mux Multiplexor
NIC Network Interface Controller
NMI Nonmaskable Interrupt
OBF Output Buffer
OEM Original Equipment Manufacturer
Ohm Unit of electrical resistance
PEF Platform Event Filtering
PEP Platform Event Paging
PIA Platform Information Area (This feature configures the firmware for the platform hardware)
PLD Programmable Logic Device
PMI Platform Management Interrupt
POST Power-On Self Test
PSMI Power Supply Management Interface
PWM Pulse-Width Modulation
RAM Random Access Memory
RASUM Reliability, Availability, Serviceability, Usability, and Manageability
RISC Reduced Instruction Set Computing
ROM Read Only Memory
RTC Real-Time Clock (Component of ICH peripheral chip on the server board)
SDR Sensor Data Record
SECC Single Edge Connector Cartridge
SEEPROM Serial Electrically Erasable Programmable Read-Only Memory
SEL System Event Log
Revision 1.2
Intel order number: D41763-003
119