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Intel® Server Boards S5000PSL and S5000XSL TPS List of Tables
3.1 Intel
®
5000P / 5000X Memory Controller Hub (MCH)
The Memory Controller Hub (MCH) is a single 1432-pin FCBGA package, which includes the following core platform functions:
System Bus Interface for the processor sub-system
Memory Controller
PCI-Express Ports including the Enterprise South Bridge Interface (ESI)
FBD Thermal Management
SMBUS Interface
This section provides a high-level overview of some of these core functions as they pertain to this server board. Additional
information can be obtained from the Intel S5000 Server Board Family Datasheet and the Intel 5000 Series Chipset Memory
Controller Hub Datasheet.
3.1.1 System Bus Interface
The MCH is configured for symmetric multi-processing across two independent front side bus interfaces that connect to the Dual-
Core Intel
®
Xeon
®
processors. Each front side bus on the MCH uses a 64-bit wide 667, 1066, or 1333-MHz data bus. The 1333-MHz
data bus is capable of transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of addressing up
to 64 GB of memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one processor on each
bus.
3.1.2 Processor Support
The server board supports one or two Dual Core Intel
®
Xeon
®
processors 5000 sequence, with system bus speeds of 667 MHz, 1066
MHz, and1333 MHz, and core frequencies starting at 3.73 GHz. Previous generations of the Intel
®
Xeon
®
processor are not
supported on this server board.
Note: Only Dual Core Intel
®
Xeon
®
processors 5000 Sequence that support system bus speeds of 667 MHz, 1066 MHz and 1333
MHz are supported on this server board. See the following table for a list of supported processors.
Table 2. Processor Support Matrix
Processor Family System Bus Speed Core Frequency Cache Watts Support
Intel
®
Xeon
®
Processor 5030 667MHz 2.67 GHz 2x 2 MB 95 Yes
Revision 1.2
Intel order number: D41763-003
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