Filter
Top Products
© National Instruments Corp. 3-1 GPIB-BUF User Manual
Chapter 3
Technical Information
This chapter contains a more detailed description of the operation of the
GPIB-BUF. The timing characteristics of the parallel port are provided in
this chapter.
The GPIB-BUF is actually a powerful 8-bit microcomputer tailored for use
as an IEEE 488 data buffer. The operating system of the unit is contained in
Read-Only Memory (ROM) and can address up to 1 MB of dynamic
Random Access Memory (RAM). The GPIB-BUF microprocessor contains
an integrated Direct Memory Access (DMA) Controller for high-speed data
transfers from the GPIB circuitry. The processor also contains an integrated
memory management unit, a dynamic RAM Controller, a clock generator, a
programmable timer unit, a full duplex UART, and an interrupt Controller.
Two LSI GPIB Controller chips which are programmed and maintained by
the operating system provide all GPIB functionality. Both controller chips
are connected to their respective ports through GPIB transceivers which are
responsible for guaranteeing that the electrical characteristics of the
IEEE 488 specification are upheld.
Power Up
When powered on, the GPIB-BUF runs internal diagnostics to verify the
operation of all internal circuitry. Since the diagnostics can take as long as
20 s, the READY LED blinks during the test to indicate that the power-on
self-test is progressing successfully. If no errors are found, the GPIB-BUF
illuminates the READY and EMPTY LEDs which indicates that the
GPIB-BUF is ready to operate and its internal data buffer is empty. If the
GPIB-BUF is in listen-only mode, it also illuminates the LISTEN LED at
this time.
After the GPIB-BUF has successfully completed its power-on self-test, it
asserts the Interface Clear (IFC *) signal on the GPIB OUT port to initialize
the link between the GPIB-BUF and the target device, and to establish the
ability of the GPIB-BUF to address the target device. The GPIB-BUF then
reads the status of the configuration switches and initializes the rest of the
system.