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DDR3THIN-MN-XXX 30 Doc. Rev. 1.11
Group
Name
Signal
Name
DDR3
Pin #
TLA
Input
Group
Name
Signal
Name
DDR3
Pin #
TLA
Input
Control
2
cCKE1 From Slot C M_E3:5 Address
2
BA2 52 M_A3:0
(SYM) cCKE0 From Slot C M_E3:4 (Hex) BA1 190 M_C3:7
bCLK1 From Slot B M_Q2 BA0 71 M_C1:6
bCLK0 From Slot B M_E1:7 A15 171 M_CK0
CKE1 169 M_A3:2 A14 172 M_A2:5
CKE0 50 M_A3:1 A13 196 M_CK3
cS1# From Slot C M_E2:6 A12/BC# 174 M_A2:4
cS0# From Slot C M_E2:2 A11 55 M_A2:6
bS1# From Slot B M_E0:4 A10/AP 70 M_C1:3
bS0# From Slot B M_E0:0 A9 175 M_A2:1
S3# 49 M_C2:5 A8 177 M_A2:0
S2# 48 M_C3:0 A7 56 M_A2:3
S1# 76 M_C3:4 A6 178 M_C0:3
S0# 193 M_C3:3 A5 58 M_A2:2
BA2 52 M_A3:0 A4 59 M_C0:5
BA1 190 M_C3:7 A3 180 M_C1:0
BA0 71 M_C1:6 A2 61 M_Q1
A15
171 M_CK0 A1 181 M_C1:1
A14 172 M_A2:5 A0 188 M_C1:5
A13 196 M_CK3 Strobes DQS7 111 S_A2:6
A12/BC# 174 M_A2:4 (HEX) DQS6 103 S_A3:5
A10/AP 70 M_C1:3 DQS5 94 S_CK1
RAS# 192 M_C3:6 DQS4 85 M_C2:3
CAS# 74 M_C3:5 DQS3 34 M_A0:1
WE# 73 M_C1:7 DQS2 25 S_C3:0
Misc
2
MISC1
Placeholder
M_A3:5 DQS1 16 S_E3:6
(OFF) MISC0
Placeholder
M_A3:4 DQS0 7 S_E2:4
DDRCK0+/- 184/185 M_C1:4 Ungrouped DQS8 43 M_A1:2
Unprobed All DQSx# 1_DQS8 43 S2_D3:2
DDRCK1+/- 63/64 DM8 161 M_A1:1
SA1 237 ERR_OUT#³ 53 M_A2:7
SDA 238 RESET# 168 M_A3:6
SA0 117 TEST 167 M_A3:7
SCL 118 ODT0 195 M_C2:0
ODT1 77 M_C2:1
PAR_IN 68 M_C1:2
Table 2 – B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.)
Notes:
1. ‘ # ‘ denotes a low-true signal
2. These signals are required for accurate acquisition and post-processing of acquired data
3. The ‘S’ in front of a TLA channel denotes the Slave card of the merged set
4. The ‘M’ in front of a TLA channel denotes the Master card of the merged set