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DDR3THIN-MN-XXX 33 Doc. Rev. 1.11
Group
Name
Signal
Name
DDR3
Pin #
TLA
Input
Group
Name
Signal
Name
DDR3
Pin #
TLA
Input
1_RdA_DatHi 1_RD_A_DQ63 234 S2_A0:0 1_RdA_DatLo 1_RD_A_DQ31 156 S2_D2:6
(Hex) 1_RD_A_DQ62 233 S2_A0:1 (Hex) 1_RD_A_DQ30 155 S2_D2:3
1_RD_A_DQ61 228 S2_A0:5 1_RD_A_DQ29 150 S2_E2:0
1_RD_A_DQ60 227 S2_CK1 1_RD_A_DQ28 149 S2_E2:1
1_RD_A_DQ59 115 S2_A0:2 1_RD_A_DQ27 37 S2_D2:4
1_RD_A_DQ58 114 S2_A0:3 1_RD_A_DQ26 36 S2_D2:1
1_RD_A_DQ57 109 S2_A0:7 1_RD_A_DQ25 31 S2_E2:2
1_RD_A_DQ56 108 S2_A1:0 1_RD_A_DQ24 30 S2_E2:3
1_RD_A_DQ55 225 S2_A1:2 1_RD_A_DQ23 147 S2_E2:4
1_RD_A_DQ54 224 S2_A1:3 1_RD_A_DQ22 146 S2_E2:5
1_RD_A_DQ53 219 S2_A1:7 1_RD_A_DQ21 141 S2_E3:2
1_RD_A_DQ52 218 S2_D1:5 1_RD_A_DQ20 140 S2_E3:3
1_RD_A_DQ51 106 S2_A1:1 1_RD_A_DQ19 28 S2_E2:6
1_RD_A_DQ50 105 S2_A1:4 1_RD_A_DQ18 27 S2_E2:7
1_RD_A_DQ49 100 S2_D1:7 1_RD_A_DQ17 22 S2_E3:1
1_RD_A_DQ48 99 S2_D1:6 1_RD_A_DQ16 21 S2_E3:4
1_RD_A_DQ47 216 S2_D1:4 1_RD_A_DQ15 138 S2_E3:6
1_RD_A_DQ46 215 S2_D1:1 1_RD_A_DQ14 137 S2_E3:7
1_RD_A_DQ45 210 S2_D0:7 1_RD_A_DQ13 132 S2_E1:4
1_RD_A_DQ44 209 S2_D0:6 1_RD_A_DQ12 131 S2_E1:1
1_RD_A_DQ43 97 S2_D1:3 1_RD_A_DQ11 19 S2_E3:5
1_RD_A_DQ42 96 S2_D1:2 1_RD_A_DQ10 18 S2_E1:7
1_RD_A_DQ41 91 S2_D0:5 1_RD_A_DQ9 13 S2_E1:3
1_RD_A_DQ40 90 S2_D0:4 1_RD_A_DQ8 12 S2_E1:2
1_RD_A_DQ39 207 S2_D0:3 1_RD_A_DQ7 129 S2_E1:0
1_RD_A_DQ38 206 S2_D0:2 1_RD_A_DQ6 128 S2_E0:7
1_RD_A_DQ37 201 S2_C2:1 1_RD_A_DQ5 123 S2_E0:3
1_RD_A_DQ36 200 S2_C2:4 1_RD_A_DQ4 122 S2_E0:2
1_RD_A_DQ35 88 S2_D0:1 1_RD_A_DQ3 10 S2_Q2
1_RD_A_DQ34 87 S2_D0:0 1_RD_A_DQ2 9 S2_E0:5
1_RD_A_DQ33 83 S2_C2:6 1_RD_A_DQ1 4 S2_E0:1
1_RD_A_DQ32 81 S2_C2:7 1_RD_A_DQ0 3 S2_E0:0
Table 3 – B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.)
Notes:
1. These signals are acquired from the second DIMM slot
2. All signals on this page are required for accurate post-processing of acquired data
3. The ‘S2’ in front of a TLA channel denotes Slave card #2 of the merged set