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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 176 SMSC LAN9312
DATASHEET
4 RX Status FIFO Full Interrupt (RSFF)
This interrupt is generated when the RX Status FIFO is full.
R/WC 0b
3
RX Status FIFO Level Interrupt (RSFL)
This interrupt is generated when the RX Status FIFO reaches the
programmed level in the RX Status Level field of the FIFO Level Interrupt
Register (FIFO_INT).
R/WC 0b
2:0
RESERVED RO -
BITS DESCRIPTION TYPE DEFAULT