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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 374 SMSC LAN9312
DATASHEET
14.5.3.7 Switch Engine ALR Configuration Register (SWE_ALR_CFG)
This register controls the ALR aging timer duration.
Register #: 1809h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:1 RESERVED RO -
0
ALR Age Test
When set, this bit decreases the aging timer from 5 minutes to 50mS.
R/W 0b