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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 202 SMSC LAN9312
DATASHEET
14.2.5.2 Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x)
Note: The selection between Sync or Delay_Req packets is based on the corresponding
master/slave bit in the 1588 Configuration Register (1588_CONFIG).
Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to
Section 14.2.5 for additional information.
Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to
the switch fabric.
Offset: Port 1: 104h Size: 32 bits
Port 2: 124h
Port 0: 144h
BITS DESCRIPTION TYPE DEFAULT
31:0 Timestamp Low (TS_LO)
This field contains the low 32-bits of the timestamp taken on the receipt of
a 1588 Sync or Delay_Req packet.
RO 00000000h