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120 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
muli
Multiply Immediate
Description
Multiplies the contents of registers rA and the value IMM, sign-extended to 32 bits; and
puts the result in register rD. This is a 32-bit by 32-bit multiplication that will produce a 64-
bit result. The least significant word of this value is placed in rD. The most significant word
is discarded.
Pseudocode
(rD) ← LSW( (rA) × sext(IMM) )
Registers Altered
• rD
Latency
1 cycle
Notes
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32
bits to use as the immediate operand. This behavior can be overridden by preceding the
Type B instruction with an imm instruction. See the imm instruction for details on using
32-bit immediate values.
This instruction is only valid if the target architecture has multiplier primitives, and if
present, the MicroBlaze parameter C_USE_HW_MUL is set to 1.
muli rD, rA, IMM
0 1 1 0 0 0 rD rA IMM
0 6 11 16 31