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MicroBlaze Processor Reference Guide www.xilinx.com 41
UG081 (v6.0) June 1, 2006 1-800-255-7778
Floating Point Unit (FPU)
R
Format
An IEEE 754 single precision floating point number is composed of the following three
fields:
1. 1-bit sign
2. 8-bit biased exponent
3. 23-bit fraction (a.k.a. mantissa or significand)
The fields are stored in a 32 bit word as defined in Figure 1-11:
The value of a floating point number v in MicroBlaze has the following interpretation:
1. If exponent = 255 and fraction <> 0, then v= NaN, regardless of the sign bit
2. If exponent = 255 and fraction = 0, then v= (-1)
sign
* ∞
3. If 0 < exponent < 255, then v = (-1)
sign
* 2
(exponent-127)
* (1.fraction)
4. If exponent = 0 and fraction <> 0, then v = (-1)
sign
* 2
-126
* (0.fraction)
5. If exponent = 0 and fraction = 0, then v = (-1)
sign
* 0
For practical purposes only 3 and 5 are really useful, while the others all represent either an
error or numbers that can no longer be represented with full precision in a 32 bit format.
Rounding
The MicroBlaze FPU only implements the default rounding mode, “Round-to-nearest”,
specified in IEEE 754. By definition, the result of any floating point operation should return
the nearest single precision value to the infinitely precise result. If the two nearest
representable values are equally near, then the one with its least significant bit zero is
returned.
Operations
All MicroBlaze FPU operations use the processors general purpose registers rather than a
dedicated floating point register file, see “General Purpose Registers”.
Arithmetic
The FPU implements the following floating point operations:
• addition, fadd
• subtraction, fsub
• multiplication, fmul
• division, fdiv
01 9 31
↑↑ ↑
sign exponent fraction
Figure 1-11: IEEE 754 Single Precision format