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MicroBlaze Processor Reference Guide www.xilinx.com 75
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
and
Logical AND
Description
The contents of register rA are ANDed with the contents of register rB; the result is placed
into register rD.
Pseudocode
(rD) ← (rA) ∧ (rB)
Registers Altered
• rD
Latency
1 cycle
and rD, rA, rB
1 0 0 0 0 1 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31